As graphics applications have increased in complexity and realism, the capabilities of host platforms (including processor speeds, system memory capacity and bandwidth, and multiprocessing) are also continually increasing. To meet the demands of modern graphics, graphics controllers, sometimes also called graphics accelerators, have become an integral component in present day computer systems. In the present disclosure, the term graphics controller refers to either a graphics controller or graphics accelerator. In computer systems, graphics controllers control the display subsystem of a computer such as a personal computer, workstation, personal digital assistant (PDA), or any kind of equipment with a display monitor.
When only display pixel data was processed in a graphics controller, the occurrence of an error in the graphics display did not stop the computer system from operating. With increased demands on the display subsystem, graphics controllers now process graphics commands and errors in these commands can affect more than just the display of graphics. Because prior art graphics controllers have treated commands the same as data, these graphic controllers do not have fault tolerant capability with regard to errors in graphics commands. That is, the conventional graphics controller does not correct the errors in the digital commands it receives. In a typical command error situation, a computer system display may operate erratically, and, in a worse case situation, the entire computer system may fail, thus necessitating a reboot of the system. Additionally, because prior art graphics controllers do not provide for error detection or correction they cannot provide any diagnostic information to the host computer system.
Commonly a graphics controller includes a memory for use as a frame buffer for the display. This frame buffer memory is somewhat prone to error, especially when implemented with dynamic random access memory (DRAM).
Moreover, with the advent of high speed data transfer rates, for example, data rates over 500 mega-transfers per second (MT/sec) between a chip and an external DRAM, errors can be much more common. Errors can be caused from timing, voltage and noise problems. Moreover, simply moving a pad or wire on an integrated circuit (IC) design can sometimes dramatically increase the occurrence of errors. Thus, prior art graphics controllers are not fault tolerant. Moreover, any error occurring anywhere within a command transfer flow (e.g., in a first-in-first-out (FIFO) device, DRAM, high speed printed circuit board pad or trace, etc.) can cause the computer system to fail. In such a situation, a graphics controller, computer system or operating system does not have information that an error has occurred and further does not have a manner for detecting that an error has occurred within the graphics controller. Without knowledge of an error and further, without knowledge of where an error occurred, the computer system can, of course, not take corrective action. In prior art computer systems, an error within a graphics controller can be such that the entire computer system fails without possibility of recovery. The only real manner of correcting such an error may be to reset or reboot the host computer system.
Thus, it would be desirable to have an improved graphics controller that can tolerate errors in its commands.